Various types of personalizable integrated circuits and programmable integrated circuits are known in the art. Personalizable integrated circuits include gate arrays, such as laser programmable gate arrays, commonly known as LPGA devices, which are described, inter alia in the following U.S. Pat. Nos. 4,924,287; 4,960,729; 4,933,738; 5,111,273; 5,260,597; 5,329,152; 5,565,758; 5,619,062; 5,679,967; 5,684,412; 5,751,165; 5,818,728. Devices of this type are personalized by etching or laser ablation of metal portions thereof.
There are also known field programmable gate arrays, commonly known as FPGA devices, programmable logic devices, commonly known as PLD devices as well as complex programmable logic devices, commonly known as CPLD devices. Devices of these type are programmable by application of electrical signals thereto.
Programmable logic devices are known in which programmable look up tables are employed to perform relatively elementary logic functions. Examples of such devices appear in U.S. Pat. Nos. 3,473,160 and 4,706,216. Multiplexers are also known to be used as programmable logic elements. Examples of such devices appear in U.S. Pat. Nos. 4,910,417, 5,341,041 and 5,781,033. U.S. Pat. Nos. 5,684,412, 5,751,165 and 5,861,641 show the use of multiplexers to perform customizable logic functions.
Problems of clock skew in gate arrays are well known. U.S. Pat. No. 5,420,544 describes a technique for reducing clock skew in gate arrays which employs a plurality of phase adjusting devices for adjusting the phase at various locations in gate arrays. Various clock tree design structures have been proposed which produce relatively low clock skew.
PCT Published Patent Application WO 98/43353 describes a functional block architecture for a gate array.
U.S. Pat. No. 5,825,202 describes an integrated semiconductor device comprising a FPGA portion connected to a maskdefined application specific logic area.